The present invention relates in general to phase-locked loops and more specifically to a phase-locked loop providing a first response during a steady-state or locked operating condition and a second response during a transient or unlocked operating condition.
The phase-locked loop (PLL) is widely used as a frequency synthesizer in radio receivers. In particular, a PLL is employed to generate a mixing signal having a commanded frequency for shifting a desired radio frequency (RF) signal to a fixed intermediate frequency (IF) signal. A variable frequency divider is employed connected between the voltage-controlled oscillator (VCO) and the PLL phase detector so that any of a number of predetermined frequencies can be selected.
For each particular value of the frequency divider, the phase-locked loop "locks-in" to maintain a fixed phase relationship between the divided VCO output signal and a reference signal. When the frequency divider is changed to a new value, the control voltage to the VCO is altered until the PLL locks at the new output frequency.
When a PLL is locked, it is desirable to reject any disturbances (other than a change in the frequency divider command) such as noise in the phase detector or the loop filter which might alter the PLL output. A loop filter with a narrow bandpass (i.e., a long time constant) is known to provide the best disturbance rejection for the PLL.
When switching to a new synthesized frequency, it is desirable to quickly lock-in at the new frequency. Fast frequency shifting is important in scan tuning operations and in radios which sample received signal strength at frequencies other than the currently received signal for comparison and selection of the best signal (e.g., as in the radio data system or RDS). It is known that the fastest frequency switching is obtained by providing a wide bandwidth (i.e., short time constant) in the loop filter. Therefore, a tradeoff has been required in designing PLL systems in order to maximize noise immunity when locked (i.e., at steady-state mode) and to minimize the response time in locking into a new frequency (i.e., at transient mode).
Some improvement in PLL characteristics has been obtained in the prior art by providing a selectable time constant for the loop filter, e.g., by using switched resistance in the filter. Specifically, the time constant is reduced (i.e., loop filter bandwidth is increased) when a variable frequency divider command is changed in order to quickly lock-on and synthesize a new output frequency. Once the new frequency is reached, the time constant is increased (i.e., loop filter bandwidth is reduced) so that frequency lock is maintained during noise disturbances or flutter in the PLL inputs. These techniques are employed, for example, in Norimatsu U.S. Pat. No. 5,113,152 and Okada U.S. Pat. No. 4,546,330.
The upper and lower time constants (i.e., the two selectable values for the upper cutoff frequency of the loop filter) that can be used in the prior art are constrained by the requirement that the feedback system be stable throughout the operating range of the PLL. In the prior art, it has not been possible to simultaneously obtain high disturbance rejection at steady-state mode and very fast (i.e., near deadbeat) frequency switching during transient mode.